![SOLVED: For a negative edge-triggered J-K flip-flop with inputs as shown in Figure 7,determine the Q output relative to the clock.Assume that Q starts LOW K For the positive edge-triggered D flip-flop SOLVED: For a negative edge-triggered J-K flip-flop with inputs as shown in Figure 7,determine the Q output relative to the clock.Assume that Q starts LOW K For the positive edge-triggered D flip-flop](https://cdn.numerade.com/ask_images/f117354f65b24f508f0ebdf97fec2133.jpg)
SOLVED: For a negative edge-triggered J-K flip-flop with inputs as shown in Figure 7,determine the Q output relative to the clock.Assume that Q starts LOW K For the positive edge-triggered D flip-flop
![This happens to be a negative edge triggered JK flip flop. I used boolean algebra and found D = E' and E = D'. Given the propagation delay I thought this was This happens to be a negative edge triggered JK flip flop. I used boolean algebra and found D = E' and E = D'. Given the propagation delay I thought this was](https://i.redd.it/cv6hms38j8051.jpg)
This happens to be a negative edge triggered JK flip flop. I used boolean algebra and found D = E' and E = D'. Given the propagation delay I thought this was
![digital logic - Confusion about when a JK flip flop is triggered - Electrical Engineering Stack Exchange digital logic - Confusion about when a JK flip flop is triggered - Electrical Engineering Stack Exchange](https://upload.wikimedia.org/wikipedia/commons/thumb/5/52/Negative-edge_triggered_master_slave_D_flip-flop.svg/337px-Negative-edge_triggered_master_slave_D_flip-flop.svg.png)
digital logic - Confusion about when a JK flip flop is triggered - Electrical Engineering Stack Exchange
![Source SN74LVC112ADR DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP MIT CLEAR UND PRESET Schaltung w on m.alibaba.com Source SN74LVC112ADR DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP MIT CLEAR UND PRESET Schaltung w on m.alibaba.com](https://sc01.alicdn.com/kf/HTB1fheqb3aTBuNjSszfq6xgfpXaN/221292105/HTB1fheqb3aTBuNjSszfq6xgfpXaN.jpg)